1 . Field of the Invention
The present invention relates generally to residual charge compensation of an electrical circuit and particularly to residual charge compensation of a circuit when operating power is momentarily interrupted.
2. Description of the Prior Art
In recent years, circuits for semiconductor integrated circuit devices have been devised in which a change of a power supply voltage is utilized for generating an output such as a pulse signal. As an example of such circuits, there is a power-on reset pulse generator circuit which detects a rise of the supply voltage above a predetermined voltage at a power-on to generate a signal (power-on reset pulse) for initializing other circuits arranged on a same chip.
FIG. 13 is a block diagram illustrating a semiconductor integrated circuit device provided with a power-on reset pulse generator circuit. Referring to FIG. 13, the power-on reset pulse generator circuit 300 is arranged on the same chip as an internal circuit 400 of the semiconductor integrated circuit device 200. The power-on reset pulse generator circuit 300 and the internal circuit 400 are connected to a power supply terminal 500 for receiving a supply voltage Vcc from an external power supply (not shown).
FIG. 13 shows internal structures of the power-on reset circuit in functional blocks. A coupling circuit 310 couples supply voltage Vcc applied to a supply terminal 500 to an input end of a latch circuit 320. The latch circuit 320 holds two potentials having usually complementary logic levels, corresponding to the potential at the input end. Either of the potentials held in the latch circuit 320 is applied to an output circuit 330 and to a delay circuit 340. Delay circuit 340 provides delay of a prescribed time period to an output signal from the latch circuit 320 and applies the output signal to a forcing circuit 350. The forcing circuit 350 inverts potential of the input end of the latch circuit 320 in response to a first inversion after power-on of an output logic level of the delay circuit 340, and maintains the potential at the inverted level. By the operation of the forcing circuit 350, the output logic level of the latch circuit 320 is kept at the H level or L level for a period of time corresponding to the delay time of the signal in the delay circuit 340, immediately after the power-on. The output circuit 330 converts the output signal from the latch circuit 220 to a signal POR or POR which has a logic level enabling initialization of the circuit 400 immediately after the power-on only, and outputs the same.
In this way, the power-on reset pulse generator circuit 300 is responsive to the power-on to generate a signal POR or POR for initializing the internal circuit 400. The internal circuit 400 is driven by a supply voltage Vcc supplied from the supply terminal 500, and starts a normal operation after it is initialized while the power-on reset pulse generator circuit 300 is generating the pulse signal POR or POR for the initialization. This initialization forces a potential at a predetermined node in the internal circuit 400 to a potential (referred to as an initial potential) to be maintained at the start of the ordinary operation. Therefore, unless the power-on reset pulse generator circuit 300 generates the power-on reset pulse having a sufficient level and width, the above predetermined node in the internal circuit 400 is not sufficiently set at the initial potential, resulting in problems such as a malfunction of the internal circuit 400.
FIG. 9 is an actual circuit diagram illustrating internal structures of the power-on reset pulse generator circuit 300 shown in FIG. 13. The structures and operations of this power-on reset pulse generator circuit will be described hereinafter.
Referring to FIG. 9, this power-on reset pulse generator circuit includes inverters 11 and 12 which form a flip-flop 101, two diode-connected N-channel MOS transistors D11 and D12 which form a MOS diode array 102, a capacitor C11 connected between the flip-flop 101 and the supply terminal 500, and inverters 13 and 14 connected in series between the flip-flop 101 and a POR output terminal A10. This power-on reset pulse generator circuit further includes a capacitor C12 connected between an input terminal of the inverter 12 and the ground GND, an N-channel MOS transistor T12 provided between the capacitor C11 and the ground GND, a capacitor C13 connected in parallel between a gate of the transistor T12 and the ground GND, and an N-channel MOS transistor T11. The MOS diode array 102 is provided between an output terminal of the inverter 14 and the gate of the transistor T12.
Now, operations of this power-on reset pulse generator circuit will be described, assuming that the power supply is turned on when the nodes N11-N14 in this power-on reset circuit have potentials of 0 V (0 volt) owing to sufficient discharge. The following description will be given with reference to FIGS. 10 and 11. FIG. 10 is a circuit diagram more specifically illustrating the structures of the power-on reset pulse generator circuit in FIG. 9. FIG. 11 is a waveform diagram illustrating the operations of the power-on reset pulse generator circuit when each node in the power-on reset pulse generator circuit has the potential of 0 V.
Referring to FIG. 10, the inverters 11-14 are respectively formed of P-channel MOS transistors 110, 120, 130 and 140 which are connected in series between the supply terminal 500 and the ground GND as well as N-channel MOS transistors 111, 121, 131 and 141 which are connected between the supply terminal 500 and the ground GND.
Referring to FIGS. 10 and 11, when the power supply is turned on at a time t20, the supply voltage Vcc ((a) in FIG. 11) rises from 0 V to, e.g., 5 V. In this operation, since the transistor T12 is in an OFF state, the potential ((b) in FIG. 11) of the node N11 rises along with the supply voltage Vcc owing to coupling of the capacitor C11. Meanwhile, the capacitor C12 of the node N12 tends to maintain the potential before the power-on, i.e., of 0 V. Therefore, the flip-flop 101 is set such that the output terminal of the inverter 12 has the potential at the H level.
After power-on, until the potential at the node N11 (FIG. 11(b)) reaches the threshold voltage V.sub.th of the transistor 130, the transistor 130 is ON in the inverter 13, and therefore the potential at the node N13 (FIG. 11(d)) rises together with the supply voltage Vcc, in response to the power-on. When the potential at the node N11 exceeds the threshold voltage V.sub.th, the transistor 130 in the inverter 13 is turned OFF, and in turn, the transistor 131 is turned ON, so that the potential at the node N13 lowers to 0 V. In this manner, the potential at the node N13 rises together with the supply voltage Vcc to the threshold voltage Vth after the power-on, and then returns to 0 V. Therefore, after the power-on, the transistor 140 in the inverter 14 is ON, and hence the potential at the output terminal A10 (FIG. 11(e)) rises together with the supply voltage Vcc.
When the potential at the node N13 is at the L level (=O V), the transistor T11 is in the OFF state, so that the potential at the node N14 depends on the potential of the output terminal A10. When the potential at the output terminal A10 exceeds a sum (2 Vth) of the threshold voltages Vth of the transistors D11 and D12 which form the diode array 102, both the transistors D11 and D12 are turned on, and accordingly the potential ((f) in FIG. 11) at the node N14 rises to a potential (Vcc-2 Vth) which is lower than the supply voltage Vcc by the threshold voltage (2 Vth) of the diode array 102. When the potential at the node N14 exceeds the threshold voltage Vth of the transistor T12 at the time t21, the transistor T12 is also turned on. Consequently, the charges supplied from the supply terminal 500 to the node N11 owing to the coupling of the capacitor C11 are discharged to the ground GND. This discharge at the node N11 turns on the transistors 110 and 121 in the inverts 11 and 12 of the flip-flop 101, so that the flip-flop 101 is reset. Thus, the potential at the node N12 is set at the H level by the charges supplied to the node N12 from the supply terminal 500 through the transistor 110. In response to the node N11 having the potential at the L level, the transistors 130 and 141 in the inverters 13 and 14 become conductive. Consequently, the potential at the node N13 rises to the potential of the supply voltage Vcc to be set at the H level, and then the potential at the output terminal A10 falls to the ground potential (=0 V). Meanwhile, in response to the output (node N13) of the inverter 13 having the potential at the H level, the transistor T11 becomes conductive and lowers the potential at the node N14 to 0 V. Therefore, the transistor T12 is again set to the OFF state. The potential are the node N11 is, however, maintained at the L level by the transistor 121 in the inverter 12. Accordingly, the potentials at the nodes N12 and N13 are raised to 5 V by the transistors 110 and 130 which are on in accordance with the rise of the supply voltage Vcc, and the potential at the output terminal A10 is fallen to 0 V by the transistor 141 which in on thereafter.
In the power-on reset pulse generator circuit, as described above, if the delay due to the charge and discharge during the change of the potentials at the respective nodes is neglected, the potential at the terminal A10 is kept at the H level for the period of time until the rising supply voltage Vcc exceeds the sum (3 Vth) of the threshold voltage 2 Vth of the diode array 102 and the threshold voltage Vth of the transistor T12, and it falls to the L level when the supply voltage Vcc exceeds 3 Vth thereafter. Thus, the terminal A10 receives the pulse signal at the H level for the predetermined period in response to the power-on. More specifically, it receives a power-on reset pulse POR which is kept at the H level for the predetermined period in response to the power-on.
FIG. 14 is a block diagram showing a structure of a conventional power-on reset pulse generating circuit generating a power-on reset pulse POR of negative polarity, in accordance with the same principle as that of the power-on reset pulse generating circuit shown in FIG. 9.
Referring to FIG. 14, different from the circuit shown in FIG. 9, in this power-on reset circuit, an output of an inverter 11 in a flip flop 101 is input to an inverter 13, an output from the inverter 13 is applied to a diode array 102, and an output of an inverter 14 is input to a gate of a transistor T11.
Now, operations of this power-on reset pulse generator circuit will be described, assuming that the power supply is turned on when the nodes N11-N14 in this power-on reset circuit have potentials of 0 V (0 volt) owing to sufficient discharge. The following description will be given with reference to FIGS. 15 and 16. FIG. 15 is a circuit diagram more specifically illustrating the structure of the power-on reset pulse generator circuit in FIG. 14. FIG. 16 is a waveform diagram illustrating the operations of the power-on reset pulse generator circuit when each node in the power-on reset pulse generator circuit has the potential of 0 V.
Referring to FIGS. 15 and 16, when the power supply is turned on at a time t20, the supply voltage Vcc ((a) in FIG. 16) rises from 0 V to, e.g., 5 V. IN this operation, since the transistor T12 is in an OFF state, the potential ((b) in FIG. 16) of the node N11 rises along with the supply voltage Vcc owing to coupling of the capacitor C11. Meanwhile, the capacitor C12 of the node N12 tends to maintain the potential before the power-on, i.e., of 0 V. Therefore, the flip-flop 101 is set such that the output terminal of the inverter 12 has the potential at the H level.
The node N12 has the potential at an L level ((c) i FIG. 16) when the power supply is turned on. Therefore, the transistor 130 in the inverter 13 is turned on so that the potential ((d) in FIG. 11) of the node N13 rises along with the supply voltage Vcc to the H level in response to the power-on. In response to the potential at the H level at the node N13, the transistor 141 in the inverter 14 is turned on so that the potential ((e) in FIG. 16) at the output terminal A12 is at the L level (=0 V) immediately after the power-on.
When the potential at the output terminal A12 is at the L level the transistor T11 is in the OFF state, so that the potential at the node N14 depends on the potential of the node N13. When the potential at the node N13 exceeds a sum (2 Vth) of the threshold voltages Vth of the transistors D11 and D12 which form the diode array 102, both the transistors D11 and D12 are turned on, and accordingly the potential ((f) in FIG. 16) at the node N14 rises to a potential (Vcc-2 Vth) which is lower than the supply voltage Vcc by the threshold voltage (2 Vth) of the diode array 102. When the potential at the node N14 exceeds the threshold voltage Vth of the transistor T12 at the time t21, the transistor T12 is also turned on. Consequently, the charge supplied from the supply terminal 500 to the node N11 owing to the coupling of the capacitor C11 are discharged to the ground GND. This discharge at the node N11 turns on the transistors 110 and 121 in the inverts 11 and 12 of the flip-flop 101, so that the flip-flop 101 is reset. Thus, the potential at the node N12 is set at the H level by the charges supplied to the node N12 from the supply terminal 500 through the transistor 110. In response to the node N12 having the potential at the H level, the transistors 131 and 140 in the inverters 13 and 14 become conductive. Consequently, the potential at the node N13 is set at the L level, and then the potential at the output terminal A10 rises to the potential of the supply voltage Vcc. In response to the output (output terminal A10) of the inverter 14 having the potential at the H level, the transistor T11 becomes conductive and lowers the potential at the node N14 to 0 V. Therefore, the transistor T12 is again set to the OFF state. The potential at the node N11 is, however, maintained at the L level by the transistor 121 in the inverter 12. Accordingly, the potentials at the node N12 and the output terminal A10 are raised to 5 V by the transistors 110 and 140 which are on in accordance with the rise of the supply voltage Vcc.
in the power-on reset pulse generator circuit, as described above, if the delay due to the charge and discharge during the change of the potentials at the respective nodes is neglected, the potential at the terminal A10 is kept at the L level for the period of time until the rising supply voltage Vcc exceeds the sum (3 Vth) of the threshold voltage 2 Vth of the diode array 102 and the threshold voltage Vth of the transistor T12, and it rises to the H level when the supply voltage Vcc exceeds 3 Vth thereafter. Thus, the terminal A10 receives the pulse signal at the L level for the predetermined period in response to the power-on. More specifically, it receives an inverted signal POR of the power-on reset pulse POR which is kept at the H level for the predetermined period in response to the power-on.
The signal POR (or POR) introduced to the output terminal A10 in FIGS. 9 and 14 is used to reset the unstable nodes, which have a possibility to be at either the H level or the L level after the power-on, to the predetermined levels.
The power-on reset pulse generator circuits described above are typical examples of the conventional circuits utilizing the change of the supply voltages, and they are formed without taking residual charges at the power-off into consideration. Therefore, these residual charges adversely affect such circuits to cause the malfunction, and thus adversely and seriously affect the semiconductor integrated circuit devices including these circuits.
Referring to FIGS. 10 and 15, the operation principle of the conventional power-on reset pulse generator circuits is based on the assumption that the potentials at all the nodes in the power-on reset pulse generator circuit are of 0 V before the power-on. However, the power supply may be continuously and repetitively turned on and off, e.g., for the function test of the semiconductor integrated circuit device, or the power supply may momentarily turned off due to power failure. In these cases, the period between the power-off and the next power-on is extremely short. In such cases, the electrical charges in ones of the nodes in the power-on reset pulse generator circuit are not fully discharged, so that such a phenomenon has actually occurred that the potential in the node to be of 0 V may be shifted to the positive or negative at the next power-on. The phenomenon causes the problem as described above. This problem will be specifically described below with reference to, for instance, the power-on reset pulse generator circuits in FIG. 10 and 15.
First, this problem will be described with reference to the power-on reset pulse generator circuit in FIG. 10. In the following, reference is also made to FIG. 12, which is a waveform diagram illustrating the potential changes at the output terminal A10 and the nodes N11-N14 after the power-on when the residual charges at the last power-off have remained in the power-on reset pulse generator circuit in FIG. 10.
Referring to FIGS. 10 and 12, before a power-off time t22, the nodes N11 and N14 and the output terminal A10 have the potentials of 0 V as indicated by (b), (f) and (e) in FIG. 12, respectively, and the potentials at the node N14 and the node N13 are the supply voltage of 5 V as indicated by (c) and (d) in FIG. 12, respectively. When the power is turned off at the time t22, the supply voltage Vcc decreases from 5 V toward 0 V as indicated by (a) in FIG. 12. For the period before the time t23 at which the supply voltage Vcc lowers to the threshold voltage Vth of the MOS transistor, the potentials at the node N12 and the node N13, which have been held at the H level before the power-off, lower in accordance with the lowering of the supply voltage Vcc owing to the ON state of the transistors 110 and 130, respectively. (See (c) and (e) in FIG. 12.)
After the time t23, the supply voltage Vcc further decreases below the threshold voltage Vth of the MOS transistor toward 0 V, in which case all of the transistors in FIG. 10 are turned off. Therefore, at the time t24 when the supply voltage Vcc lowers completely to 0 V, the potential at the node N11 lowers to -Vth owing to the negative charges supplied from the capacitor C11 to the node N11. Meanwhile, the potentials at the nodes N12 and N13 lower along with the supply voltage Vcc owing to the turned on transistor 110 and 130, respectively, until the time t23 at which the supply voltage Vcc lowers to the threshold voltage Vth of the MOS transistor. However, when all the transistors connected to the nodes N12 and N13 are turned off at the time t23, discharge paths for the charges from the respective nodes N12 and N13 are electrically cut. Therefore, for the period from the time t23 to the time 24, the potential in the node N13 is held at the potential Vth, and the discharge does not occur in the capacitor C12 so that the potential in the node N12 is also held at the potential Vth which was maintained at the time t23. Thus, the positive charges remain in the node N12.
For the period from the time t24 to the time t25 at which the power supply is turned on again, the negative and positive charges which have remained at the node N11 and the nodes N12 and N13 are gradually discharged due to a junction leak. Therefore, if there is a sufficiently long period between the power-off time t24 and the next power-on time t25, the potentials at the nodes N11, N12 and N13 return to 0 V.
However, if the period between the times t24 and t25 is relatively short, the residual charges in the nodes N11, N12 and N13 are scarcely discharged. Therefore, when the power supply is turned on again immediately after the power-off, the potentials at the node N11 and the nodes N12 and N13 at this power-on are the same as the potentials -Vth and Vth at the power-off. Thus, when the power supply is turned on again at the time t25, the potential in the node N11 is raised in accordance with the rise of the supply voltage Vcc by the positive charges which are supplied from the supply terminal 500 to the node N11 owing to the coupling of the capacitor C11. When the supply voltage Vcc reaches the threshold voltage Vth of the MOS transistor at the time t26, the potential at the node N11 returns to 0 V.
Therefore, the potential at the node N13 is kept fixed at the voltage Vth which is the potential at the power-on, from T25 to T26, since the transistor 130 in the inverter 13 is kept ON due to the low potential at the node N11.
Meanwhile, the transistor 110 in the inverter 11 is in the ON state due to the lower potential at the node N11, so that the potential at the node N12 is substantially fixed at the potential Vth as at the power-on, for the period from the time t25 to the time t26. Thus, the potential at the input terminal N11 of the flip-flop 101 is set lower than the potential at the output terminal N12 in the flip-flop 101 at the time t26. This means that the transistor 110 in the inverter 11 is turned on and the transistor 121 in the inverter 12 is turned on. Thus, the flip-flop 101 is set such that the potential at the node N12 attains to the H level in a similar manner as that at the power-off. Therefore, after the time t26, the potential at the node N12 is raised in accordance with the supply voltage Vcc by the positive charges supplied by the transistor 110 from the supply terminal 500 to the node N12. When the potential at the node N12 rises to be higher than the threshold voltage Vth, the transistor 121 in the inverter 12 is rendered conductive. Therefore, the potential at the node N11 is fixed at 0 V regardless of the rise of the supply potential Vcc after the time t26 when the potential at the node N12 reaches the threshold voltage Vth (see FIG. 12(b)). Therefore, after the time of power-on t25, the transistor 130 is kept ON in the inverter 13, and therefore, the potential at the node N13 rises from the threshold voltage Vth following the supply voltage Vcc after the time t26, as shown in FIG. 12(d). In the period until the potential at the node N13 exceeds the threshold voltage V.sub.th (from t25 to t26), the transistor 140 in the inverter 14 is ON, and therefore the potential at the output terminal A10 rises following the supply voltage Vcc. However, after the time t26 when the potential of the node N13 exceeds the threshold voltage V.sub.th, the transistor 141 in the inverter 14 is ON, and therefore the potential at the output terminal A10 is fixed at the ground potential 0 V.
In the period from t25 and t26 while the potential at the node N13 is not higher than the threshold voltage V.sub.th, the potential at the node N14 depends on the potential of the output terminal A10. However, the potential at the output terminal A10 does not exceed the sum 2 Vth of the threshold voltages of the transistors T11 and T12 in this period. Therefore, the potential at the node N14 in this period is 0 V, which is the same as the potential at the time t25 of power-on. Therefore, the potential of the node N14 is kept at the same potential 0 V at the time of power-on, in the period from t25 and t26 and in the period after the time t26 while the transistor T11 is ON (the potential at the node N13 is higher than the threshold voltage V.sub.th) (see FIG. 12(f)). Therefore, the transistor t12 is kept always OFF after the time t25 when the power is turned on again, and the potential of the node N11 changes dependent only on the potential of the node N12 after the time t25.
As described above, if the potential at the node N12 has not been sufficiently lowered to 0 V but kept at about the threshold voltage V.sub.th of the transistor 121 at the time of power-on, the potential at the node N11 soon exceeds the threshold voltage V.sub.th after the power-on, and accordingly, the potential at the output terminal A10 returns to the L level after the time of power-on t25 before it rises sufficiently, that is, when it reached the threshold value V.sub.th. The waveform represented by a chain dotted line in FIG. 12(e) shows the waveform of the signal which should be provided at the output terminal A10. Thus, the power-on reset pulse POR having a sufficient pulse width will not be introduced to the output terminal A10 in response to the power-on. Meanwhile, each of the P-channel and N-channel MOS transistors in the MOS semiconductor integrated circuit device does not operate if the supply voltage Vcc is less than the threshold voltage Vth of these MOS transistors. Therefore, if the power-on reset pulse is not output after the time t26, the internal circuit 400 (FIG. 13) in the semiconductor integrated circuit device will not be initialized. Thus, in the power-on reset pulse generator circuit in the prior art, if the period from the power-off and the next power-on is short, the output from the power-on reset pulse generator circuit have already started to rise at the time t26 when the internal circuits 400 in FIG. 13 starts to operate, after the next power-on. Consequently, the internal circuit 400 is not fully initialized, which causes the malfunction of the internal circuit 400.
Next, such a problem will be specifically described below with reference to the power-on reset pulse generator circuit in FIG. 15. In the following, reference is also made to FIG. 17, which is waveform diagram illustrating the potential changes at the output terminal A10 and the nodes N11-N14 after the power-on when the residual charges at the last power-off have remained in the power-on reset pulse generator circuit in FIG. 15.
Referring to FIGS. 15 and 17, before a power-off time t22, the nodes N11, N13 and N14 have the potentials of 0 V as indicated by (b), (d) and (f) in FIG. 17, respectively, and the potentials at the node N14 and the output terminal A10 are the supply voltage of 5 V as indicated by (c) and (e) in FIG. 17, respectively. When the power is turned off at the time t22, the supply voltage Vcc decreases from 5 V toward 0 V as indicated by (a) in FIG. 17. For the period before the time t23 at which the supply voltage Vcc lowers to the threshold voltage Vth of the MOS transistor, the potentials at the output terminal A10 and the node N12, which have been held at the H level before the power-off, lower in accordance with the lowering of the supply voltage Vcc owing to the ON state of the transistors 110 and 140, respectively. (See (c) and (e) in FIG. 17.)
After the time t23, the supply voltage Vcc further decreases below the threshold voltage Vth of the MOS transistor toward 0 V, in which case all the transistors in FIG. 15 are turned off. Therefore, at the time t24 when the supply voltage Vcc lowers completely to 0 V, the potential at the node N11 lowers to -Vth owing to the negative charges supplied from the capacitor C11 to the node N11. Meanwhile, the potential at the node N12 lowers along with the supply voltage Vcc owing to the turned on transistor 110 until the time t23 at which the supply voltage Vcc lowers to the threshold voltage Vth of the MOS transistor. However, when all the transistors connected to the node N12 are turned off at the time t23, a discharge path for the charges from the node N12 is electrically cut. Therefore, for the period from the time t23 to the time 24, the discharge does not occur in the capacitor C12 so that the potential in the node N12 is held at the potential Vth which was maintained at the time t23. Thus, the positive charges remain in the node N12.
For the period from the time t24 to the time t25 at which the power supply is turned on again, the negative and positive charges which have remained at the nodes N11 and N12 are gradually discharged due to a junction leak. Therefore, if there is a sufficiently long period between the power-off time t24 and the next power-on time t25, the potentials at the nodes N11 and N12 return to 0 V.
However, if the period between the times t24 and t25 is relatively short, the residual charges in the nodes N11 and N12 are scarcely discharged. Therefore, when the power supply is turned on again immediately after the power-off, the potentials at the nodes N11 and N12 at this power-on are the same as the potentials -Vth and Vth at the power-off. Thus, when the power supply is turned on again at the time t25, the potential in the node N11 is raised in accordance with the rise of the supply voltage Vcc by the positive charges which are supplied from the supply terminal 500 to the node N11 owing to the coupling of the capacitor C11. When the supply voltage Vcc reaches the threshold voltage Vth of the MOS transistor at the time t26, the potential at the node N11 returns to 0 V. Meanwhile, the transistor 110 in the inverter 11 is in the ON state due to the lower potential at the node N11, so that the potential at the node N12 is substantially fixed at the potential Vth as at the power-on, for the period from the time t25 to the time t26. Thus, the potential at the input terminal N11 of the flip-flop 101 is set lower than the potential at the output terminal N12 in the flip-flop 101 at the time t26. This means that the transistor 110 in the inverter 11 is turned on and the transistor 121 in the inverter 12 is turned on. Thus, the flip-flop 101 is set such that the potential at the node N12 attains to the H level in a similar manner as that at the power-off. Therefore, after the time t26, the potential at the node N12 is raised in accordance with the supply voltage Vcc by the positive charges supplied by the transistor 110 from the supply terminal 500 to the node N12. When the potential at the node N12 rises to or above the threshold voltage Vth, the transistor 131 in the inverter 13 becomes conductive. However, since the potential at the node N13 is of 0 V at the power-on time t25, the potential at the node N13 is always of 0 V after the time t25 as indicated by (d) in FIG. 17. Therefore, the time 26 when the supply voltage Vcc reaches the threshold voltage Vth, the transistor 140 in the inverter 14 becomes conductive. Therefore, at the time t26, the potential at the output terminal A10 becomes the potential Vth which is the same as the supply voltage Vcc, and rises to 5 V in accordance with the rise of the supply voltage Vcc thereafter. When the potential at the output terminal A10 reaches the threshold voltage Vth at the time t26, the transistor T11 becomes conductive. However, since the potential at the node N14 has been maintained at 0 V after the power-off time t22, it is kept at 0 V even after the time t26 no matter whether the transistor T11 is turned on or off. (See (f) in FIG. 17.)
FIG. 17(e) shows, by a chain dotted line, a signal waveform which should appear at the output terminal A10.
As described above, if the potential at the node N12 is not lowered to 0 V but is maintained approximately at the threshold voltage Vth of the transistor 131, the potential at the output terminal A10 attains to the L level only for a very short period from the power-on time t25 to the time t26 at which the supply voltage Vcc rises to the threshold voltage Vth, and will always be kept at the H level for the period after the time t26. Thus, the power-on reset pulse POR having a sufficient pulse width will not be introduced to the output terminal A10 in response to the power-on. Therefore, the same problem as that described with reference to the power-on reset pulse generator circuit in FIG. 10 also occurs, in the power-on reset pulse generator circuit in FIG. 15.
When the power is turned on again, the flip flop 101 should be set in a direction allowing the output potential of the inverter 12 to attain the H level, in order to solve this problem, and therefore, the potential at the node N12 when the power is turned on again must not be higher than the potential (=0 V) of the node N11 when the power is turned on again.
Thus, in order to solve these problems, there has been used such a method that the node N12 in which the charges remain after the power-off is grounded through a resistor. In this method, however, if a resistance of the above resistor is excessively small, a through current always flows from the node N12 toward the ground, so that the semiconductor integrated circuit device has a large consumption current. In order to avoid this, it is necessary to increase the resistance of the above resistor to some extent while maintaining it in a range which allows sufficient extraction of the residual charges from the node N12. However, when forming the resistor element on the semiconductor substrate, the resistor element having a larger resistance requires a larger layout pattern for the resistor element. Accordingly, this method for removing the residual charges disadvantageously increases the consumption power and impedes the high integration of the semiconductor integrated circuit. Further, according to this method, the potential at the node N12 when the power is turned on again is set to 0 V at the lowest, which is the potential at the node N11 when the power is turned on again. However, in order to ensure setting of the flip flop 101 in the direction allowing the output voltage of the inverter 12 to attain the H level, larger difference between the potential at the node N12 and the potential at the node N11 is preferred. If this difference becomes smaller, it becomes more difficult for the inverter 11 to determine the potential at the node N11 as the H level, and similarly, it becomes more difficult for the inverter 12 to determine the potential of the node N12 as the L level. Therefore, the above described method is not fully reliable, since there is a question whether or not the flip flop 101 is surely set to the direction allowing the output potential of the inverter 12 to attain the H level when the power is turned on again.
Another method of the prior art preventing the potential of the node N12 where charges remain after the turn off of the power, from being higher than 0 V when the power is turned on again is as follows. This method will be described with reference to FIGS. 18(a) and 18(b). Referring to FIGS. 18(a) and 18(b), in this method, a discharging circuit is connected to the node N12 where charges remain. FIGS. 18(a) and 18(b) are block diagrams showing the structure of the discharging circuit.
The discharging circuit 104 comprises, as shown in FIG. 18(a), an N channel MOS transistor T14 connected between the node N12 and the ground GND, a P channel MOS transistor T15 at a capacitor C15 connected in series to each other between a supply terminal 500 and the ground GND. A node N16 between the transistor T15 and the capacitor C15 is connected to the gates of the transistors T14 and T15. As shown in FIG. 18(b), the transistor T15 may be replaced by an N channel MOS transistor T16. In such case, the gate of the transistor T16 is connected to the supply terminal 500. The operation of the discharging circuit 104 will be described with reference to FIG. 19. FIG. 19 is a diagram of waveforms showing changes of the potential at the node N16 and the supply voltage Vcc.
When the power is turned on at t0, the supply voltage Vcc (FIG. 19(a)) begins to rise to 5 V. The potential at the node N16 is 0 V at t0, and when the supply voltage Vcc reaches the threshold voltage V.sub.th of the MOS transistor at the time t1, the transistor T15 is rendered conductive in the discharging circuit 104 of FIG. 18(a), and the transistor T16 is rendered conductive in the discharging circuit 104 of FIG. 18(b). Consequently, the potential at the node N16 attains to the threshold voltage V.sub.th which is the supply voltage Vcc at the time t1, and thereafter, it rises following the supply voltage Vcc. However, since both transistors T15 and T16 have their gates and drains (or sources) connected to each other, the potential at the node N16 is fixed at a potential (Vcc-V.sub.th) which is lower than the supply voltage Vcc by the threshold voltage V.sub.th, when the supply voltage Vcc has reached the maximum value 5 V. After the time t1, when the potential at the node N16 exceeds the threshold voltage V.sub.th, the transistor T14 is rendered conductive in response thereto, and therefore the node N12 is electrically connected to the ground GND through the transistor T14.
When the power is turned off at the time t2, the supply voltage begins to lower from 5 V. However, since the capacitor C15 serves to maintain the potential of the node N16 as it is, and discharge from the node N16 is caused only by a so called junction leak from the source drain regions of transistors T15 and T16 connected thereto, the potential at the node N16 is not abruptly decreased after the time t2 at which the power is turned off, but it is kept approximately at the potential (Vcc-V.sub.th) which is higher than the threshold voltage V.sub.th (see FIG. 19(b)) Therefore, after the power is turned off, the transistor T14 is kept ON. Therefore, the node N12 is kept electrically connected to the ground GND from the time t1 when the supply voltage Vcc reaches the threshold voltage V.sub.th until after the time t2 when the power is turned off. Charges left at the node N12 when the power is turned off are discharged to the ground GND, and accordingly, the potential at the node N12 when the power is turned on again will not be higher than 0 V.
However, even in this method, the node N12 where the charges remain is kept electrically connected to the ground GND immediately after turning on of the power until the turning off of the power, causing a through current whose magnitude is dependent on the ON resistance value of the transistor T14, flowing constantly from the node N12 to the ground GND. In addition, the potential of the node N12 is decreased to the ground potential 0 V at the lowest after the turning off of the power.
Therefore, even in this method, the problem of larger power consumption occurs as in the above described method, and the reliability in properly setting the flip flop 101 of FIGS. 10 and 15 when the power is turned on again can not be very much improved.
The principle the power-on reset pulse generator circuits shown in FIGS. 9 and 10 is disclosed in U.S. Pat. No. 4,818,904. The capacitor C11, the flip flop 101, the inverters 13 and 14, the diode array 102, and the transistors T11 and T12 in the power-on reset pulse generating circuit shown in FIGS. 9 and 14 correspond to the coupling circuit 310, the latch circuit 320, the output circuit 330, the delay circuit 340 and the forcing circuit 350 shown in FIG. 13, respectively.